The invention relates to the production of a general semiconductor substrate of relaxed Si1-xGex-on-insulator (SGOI) for various electronics or optoelectronics applications, the production of strained Si or strained SiGe field effect transistor (FET) devices on SGOI, and the production of monocrystalline III-V or II-VI material-on-insulator substrates.
Relaxed SGOI is a very promising technology as it combines the benefits of two advanced technologies: the conventional SOI technology and the disruptive SiGe technology. The SOI configuration offers various advantages associated with the insulating substrate, namely reduced parasitic capacitances, improved isolation, reduced short-channel-effect, etc. The SiGe technology also has various advantages, such as mobility enhancement and integration with III-V devices.
One significant advantage of the relaxed SGOI substrate, is to fabricate high mobility strained-Si, strained-Si1-xGex or strained-Ge FET devices. For example, strained-Si MOSFETs can be made on the SGOI substrate. The strained-Si MOSFETs on the SGOI has attracted attention because it promises very high electron and hole mobilities, which increase the speed of the electronic circuit. Other III-V optoelectronic devices can also be integrated into the SGOI substrate by matching the lattice constants of III-V materials and the relaxed Si1-xGex. For example, a GaAs layer can be grown on Si1-xGex-on-insulator where x is equal or close to 1. SGOI may serve as an ultimate platform for high speed, low power electronic and optoelectronic applications.
There are several methods for fabricating SGOI substrates and SGOI FET devices. In one method, the separation by implantation of oxygen (SIMOX) technology is used to produce SGOI. SIMOX uses a high dose oxygen implant to bury a high concentration of oxygen in a Si1-xGex layer, which will then be converted into a buried oxide (BOX) layer upon annealing at a high temperature. One of the main drawbacks is the quality of the resulting Si1-xGex film and the BOX layer. In addition, the Ge segregation during the high temperature anneal also limits the amount of Ge composition to a value that is low, such as 10%. Due to the low Ge composition, the device fabricated on those SGOI substrates has limited performance. For example, the strained-Si MOSFETs fabricated on the SGOI by the SIMOX process have limited electron or hole mobility enhancement due to the low Ge composition, since the mobility enhancement is dependent on Ge composition through the degree of the strain in the strained-Si layer.
In a second method, a conventional silicon-on-insulator (SOI) substrate is used as a compliant substrate. In this process, an initially strained Si1-xGex layer is deposited on a thin SOI substrate. Upon an anneal treatment, the strain in the Si1-xGex layer is transferred to the thin silicon film underneath, resulting in relaxation of the top Si1-xGex film. The final structure is a relaxed-SiGe/strained-Si/insulator. The silicon layer in the structure is unnecessary for an ideal SGOI structure, and may complicate or undermine the performance of devices built on it. For example, it may form a parasitic back channel on the strained-Si, or may confine unwanted electrons due to the band gap offset between the strained-Si and SiGe layer.
In a third method, a similar SGOI substrate is produced using a p++ layer as an etch stop. On a first Si substrate, a compositionally graded SiGe buffer is deposited, followed by deposition of multiple material layers including a relaxed SiGe layer, a p++ etch stop layer, and a Si layer. After bonding to a second substrate, the first substrate is removed. In an etching process, the compositionally graded SiGe buffer is etched away and etching stops at P++ etch stop layer, resulting in a relaxed-SiGe/Si/insulator structure. The presence of the silicon layer in the structure may be for the purpose of facilitating the wafer bonding process, but is unnecessary for ideal SGOI substrates. Again, the silicon layer may also complicate or undermine the performance of devices built on it. For example, it may form a parasitic back channel on this strained-Si, or may confine unwanted electrons due to the band gap offset between the Si and SiGe layer. Moreover, the etch stop of p++ in the above structure is not practical when a first graded Si1-yGey layer has a final y value larger than 0.2. This is because the etch rate of KOH will slow down dramatically when KOH reaches the Si1-yGey layer with a Ge composition larger than 0.2, and that layer is itself a very good etch stop for KOH. Therefore, KOH will not be able to remove practically all of the first compositionally graded Si1-yGey layer (when y is larger than 0.2) and the second relaxed SiGe layer, thus using a p++ layer as an etch-stop for KOH is not practical.
Other attempts include re-crystallization of an amorphous Si1-xGex layer deposited on the top of a SOI (silicon-on-insulator) substrate. Again, such a structure is not an ideal SGOI substrate and the silicon layer is unnecessary, and may complicate or undermine the performance of devices built on it. The relaxation of the resultant SiGe film and quality of the resulting structure are main concerns.
In a recent method, relaxed Si1-xGex-on-insulator is produced by using 20% SiGe layer as an etch-stop. First a compositionally graded Si1-xGex buffer (where x is less than about 0.2) and then a uniform Si1-yGey etch-stop layer (where y is larger than about 0.2) are deposited on the first substrate. Then the deposited layer is bonded to a second insulating substrate. After removing the first substrate and graded buffer layer utilizing the Si1-yGey as an etch-stop, a Si1-yGey-on-insulator (SGOI) results. The method makes use of an experimental discovery that Si1-yGey with Ge composition larger than about 20% is a good etch-stop for all three conventional Si etchant systems, KOH, TMAH and EDP, and the selectivity is better than the conventional p++ etch stop. In this method the etch-stop Si1-yGey layer is part of the final SGOI structure. However, as the Ge composition in the final SGOI structure is fixed by the etch-stop Si1-yGey, if the desired Ge composition in the final SGOI structure is much higher or lower than 0.2, the above method is not practical. If it is much lower than 0.2, for example 0.1, Si0.9Ge0.1 is not a good etch stop at all. If it is much larger than 0.2, the Ge composition difference between the etch-stop layer and surface layer in the grade buffer is too big and there is large lattice constant difference between the two layers, which prevents the growth of a relaxed etch-stop Si1-yGey layer with good quality.
From above, clearly an improved method is needed to fabricate a relaxed SGOI substrate with high Ge composition and wide range of Ge composition. An improved method is needed to fabricate strained-Si or strained-SiGe FET devices on SGOI substrate with high Ge composition.